1. Field of the Invention
The present invention relates to a semiconductor device employing a high-density interconnect substrate for packaging power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and control elements for controlling the power semiconductor elements. In particular, the present invention relates to a compact, light, high-performance semiconductor device such as a hybrid IC employing ICs as control elements.
2. Description of the Prior Art
FIG. 12A is a plan view showing a semiconductor device according to a prior art employing power semiconductor elements as well as control elements for controlling the power elements. FIG. 12B is a sectional view of the device of FIG. 12A. A metal base 101 is made of, for example, Cu. A interconnect substrate 105 is soldered onto the metal base 101. The interconnect substrate 105 is composed of a ceramic substrate 102 made of, for example, alumina, a metal layer 103 made of, for example, Cu formed on the bottom surface of the substrate 102, and a wiring pattern 104 made of, for example, Cu formed on the top surface of the substrate 102. The metal layer 103 is entirely formed on the bottom surface of the substrate 102 except the periphery thereof and is soldered to the metal base 101.
On the wiring pattern 104, power semiconductor elements 106 and control elements 107 are surface mounted. The ceramic substrate 102 electrically insulates the wiring pattern 104 from the metal base 101. The thinner the substrate 102, the better the heat dissipation performance of the power semiconductor elements 106. In consideration of mechanical strength, the substrate 102 is usually 0.6 to 0.8 millimeters thick. The wiring pattern 104 passes a large current so that the thickness thereof is about 0.3 to 0.5 millimeters. The metal layer 103 functions to reduce stress caused in the interconnect substrate 105 due to temperature changes. Accordingly, the metal layer 103 has a thickness of 0.3 to 0.5 millimeters, which is substantially equal to that of the wiring pattern 104. Minimum wiring width and intervals are dependent on the thickness of a conductor of the wiring pattern 104. The wiring pattern 104 is usually formed by isotropic wet etching. When the conductor is etched in a thickness direction, it is also etched sideward. This is unavoidable. Accordingly, when the thickness of the conductor of the wiring pattern 104 is 0.3 millimeters, the minimum wiring width and intervals must be about 0.5 millimeters. Since the number of wirings for surface mounted control elements is high, the area of the interconnect substrate 105 must be expanded.
To reduce the substrate area, a multilayer wiring structure will be effective. This structure, however, is actually impossible when the thickness of the conductor of the wiring pattern 104 is about 0.3 millimeters because a large level difference will be formed between part having a multilayer wiring pattern and part having no wiring pattern. A shield pattern to prevent malfunctions of the control elements is sometimes laid under the control elements. There is no space, however, to arrange the shield pattern under the control elements when the thickness of the conductor of the wiring pattern 104 is about 0.3 millimeters. In addition, the thickness of 0.3 millimeters of the wiring pattern makes it hard to fix the surface mounted elements onto the wiring pattern. It is also hard to apply solder resist to the wiring pattern. These problems will be solved if the wiring pattern is thin. This, however, increases wiring resistance to hardly pass a large current and produces heat to deteriorate the characteristics of the power elements. Accordingly, the wiring pattern is usually not thinned.
To solve these problems of the prior art, the devices of FIGS. 10 and 11 may be proposed to employ separate interconnect substrates for power semiconductor elements and control elements. A metal base 111 is made of, for example, Cu. A power element interconnect substrate 115 and a control element interconnect substrate 119 are soldered onto the metal base 111. The power element interconnect substrate 115 is composed of a ceramic substrate 112, a metal layer 113 formed on the bottom surface of the substrate 112, and a wiring pattern 114 made of, for example, Cu formed on the top surface of the substrate 112. The control element interconnect substrate 119 is composed of a glass epoxy substrate 116, a metal layer 117 made of, for example, Cu formed on the bottom surface of the substrate 116, and a wiring pattern 118 made of, for example, Cu formed on the top surface of the substrate 116. The metal layer 113 is entirely formed on the substrate 112 except the periphery thereof and is soldered to the metal base 111. Power semiconductor elements 120 such as IGBTs are mounted on the wiring pattern 114. The metal layer 117 of the interconnect substrate 119 is soldered to the metal base 111. Control elements 121 are mounted on the wiring pattern 118 of the interconnect substrate 119. FIGS. 10 and 11 show two different ways of electrically connecting the power and control element interconnect substrates 115 and 119 to each other. FIG. 10 electrically connects the interconnect substrates 115 and 119 to each other with jumper wires 122, while FIG. 11 electrically connects the power semiconductor elements 120 on the interconnect substrate 115 to the substrate 116 of the interconnect substrate 119 with bonding wires 123.
The wiring patterns 114 and 118 of the power and control element interconnect substrates 115 and 119 may have each a proper thickness; depending on the rated current of its own. Namely, the wiring pattern 118 for the control elements may be thinned to about 0.035 millimeters because it passes a small current. This helps make the wiring pattern 118 finer, to thereby reduce the area of the interconnect substrate 119.
The advantages and disadvantages of the devices of FIGS. 10 and 11 will be considered. The device of FIG. 10 finishes the interconnect substrates 115 and 119 at first and connects them to each other with the jumper wires 122. Accordingly, the finished substrates 115 and 119 can be tested before connecting them together with the jumper wires 122. This art of FIG. 10 is advantageous in finding defects and minimizing parts losses due to the defects but is disadvantageous in needing the additional process of electrically connecting the interconnect substrates 115 and 119 with the jumper wires 122 after mounting elements on the interconnect substrates. Consequently, this art of FIG. 10 complicates manufacturing processes and deteriorates productivity.
The device of FIG. 11 needs no additional jumper wires, and therefore, never increases the number of manufacturing processes. However, surface electrodes of the power semiconductor elements 120 on the interconnect substrate 115 are electrically disconnected until the power element interconnect substrate 115 is electrically connected to the control element interconnect substrate 119, so that it is impossible to separately test the power element interconnect substrate 115 in advance. Only after the interconnect substrates 115 and 119 are electrically connected to each other, defects will be found. Accordingly, the device of FIG. 11 will involve a larger number of parts losses than the device of FIG. 12.